1. Field of the Invention
The present invention relates to an image processing apparatus, a method of controlling the same, and a storage medium.
2. Description of the Related Art
Electric circuits capable of reconstruction such as PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Array) which are capable of changing the construction of the logic circuit are well known. In general, a change to the logic circuit of a PLD or an FPGA is realized by circuit construction information stored in a non-volatile memory such as a ROM, upon activation, being written to a configuration memory which is a volatile memory within the PLD or the FPGA. Also, because the information of the configuration memory is cleared upon a power disconnection, it is necessary to write the circuit construction information stored in the ROM into the configuration memory once again upon a power supply activation. An approach of constructing the logic circuit of a PLD or an FPGA only once in a state in which the power supply is being supplied in this way is referred to as a static reconstruction. In contrast to this, FPGAs, or the like, that are able to change the construction of the logic circuit dynamically while the logic circuit is in operation have been developed, and an approach of changing a logic circuit dynamically in this way is referred to as a dynamic reconstruction.
Also, there are FPGAs capable of rewriting only a circuit construction of a particular region rather than the circuit construction of the entire chip of the FPGA, and this kind of rewriting is referred to as a partial reconstruction. In particular, changing another circuit construction without causing the operation of a circuit that is in operation to stop is referred to as a dynamic partial reconstruction. In a dynamic partial reconstruction, upon a dynamic reconstruction, it is possible to reconstruct a logic circuit of the FPGA partially by rewriting only a portion of the regions of the configuration memory rather than rewriting all of the configuration memory. By employing such a dynamic partial reconstruction, it is possible to implement a plurality of logic circuits that can be switched time-divisionally in the regions of the FPGA, for example. As a result, it is possible to flexibly realize various functions with few hardware resources while maintaining high speed computational capabilities of the hardware.
However, while it is possible to change the circuit construction in operation, the time required for changing (rewriting) of the circuit construction is long, and the time is proportional to the size of the logic circuit configuration information written to the configuration memory. Techniques have been proposed for reducing the circuit construction rewrite time.
In Japanese Patent Laid-Open No. 2012-234337, a technique is disclosed in which processing having a high possibility of being processed next is estimated in image processing, and configuration data that realizes the processing estimated to be next is loaded into high speed configuration memory in advance in order to reduce conventional rewrite times. By loading in advance, the circuit construction data load time during image processing can be reduced, and image processing speeds can be optimized.
Also, an image processing apparatus such as an MFP (Multi-Function Printer) can select from a plurality or processes (a copy job, a print job, a SEND job, or the like) in accordance with a request from a user, and these image processes are realized by hardware or software. Also, in recent years, MFPs are made to have a power saving state for reasons of power consumption reduction, and have functions for transitioning into the power saving state in cases where there is no access to the MFP for a fixed time period, and for returning from the power saving state when once again the MFP is used. In particular, there is demand for the time period for recovery from the power saving state to be such that recovery is performed in as short a time period as possible, so that the MFP immediately is made to be useable, and thereby the convenience of the user is enhanced.
However, there is a problem with the above described conventional techniques as recited below. For example, in a case in which a reconstruction is performed having estimated processing to have a high possibility of being processed next in the image processing, it is possible to optimize image processing configuration data rewrite times as in the above described conventional technique. However, there is a problem in that because upon return from the power saving state, the processing content of the image processing that operates after return is determined, and after that the configuration data is reconstructed, the time period for return from the power saving state cannot be optimized.